The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. In particular, the invention provides a method and system for determining an intrinsic device characteristic such as breakdown voltage by measuring one or more extrinsic characteristics of an MOS transistor device in an advanced integrated circuit. More particularly, the invention provides a method and device for testing a gate oxide integrity for semiconductor integrated circuit devices, but it would be recognized that the invention has a much broader range of applicability.
Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Conventional integrated circuits provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of integrated circuits.
Increasing circuit density has not only improved the complexity and performance of integrated circuits but has also provided lower cost parts to the consumer. An integrated circuit or chip fabrication facility can cost hundreds of millions, or even billions, of U.S. dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of integrated circuits on it. Therefore, by making the individual devices of an integrated circuit smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in integrated fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. Additionally, as devices require faster and faster designs, process including testing limitations exist with certain conventional processes and testing procedures for wafer reliability.
An example of such test procedure is commonly called wafer level reliability testing, commonly called WLR. In particularly, WLR has been more and more popular in process control due to the lower overall cost and the shorter cycle time for process improvement. Among the many WLR test methods, the ramp tests (voltage as well as current) take much shorter time than the traditional methods, for example, time-dependent dielectric breakdown (TDDB) testing, and isothermal EM (Iso-EM) test for the FEOL (Front-End Of Line) and BEOL (Back-End Of Line) process, respectively. In conventional GOI (Gate Oxide Integrity) V-ramp tests, we stress ramp voltage to detect breakdown voltage (Vbd) and from the Vbd values, we divide the failures into various categories.
As the technology marches into the sub-90 nm era, the gate oxide becomes thinner (<12 Å) for MOS transistors, and the leakage current increases sharply. GOI testing becomes very difficult or even impossible. That is, larger structures cannot be used for testing. Additionally, smaller structures are often difficult to test efficiently and accurately. For accurate test results using smaller samples, increased test times must often occur. These and other limitations can be found throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.